A Short Answer
Error (12007): Top-level design entity "alt_ex_1" is undefined
The error message is far from trivial to make sense of, but in a roundabout
way it does tell what is wrong.
You are (probably) using alt_ex_1.vhd as the name of your design file.
In Altera Quartus, the file name must be the same as the name of the
(top level) entity declared in the VHDL design code.
What you need to do is to change the file name from alt_ex_1.vhd to
light.vhd.
To keep it simple, create a new project named light instead of alt_ex_1.
An Elaborated Answer
Reproducing the error is straightforward. Here is what I did. 1
After starting the Quartus Prime Lite Edition click File >
New Project Wizard....
If you see an Introduction, click Next >. Choose a working directory.
As name of the project enter alt_ex_1.
Click Next > twice and then Finish.
Create a design file: File > New....
Under Design Files, choose VHDL File, then OK.
Next File > Save As.... Type or paste alt_ex_1.vhd and click
Save.
Paste the code:
library ieee;
use ieee.std_logic_1164.all;
entity light is
port(x1, x2: in std_logic;
f: out std_logic);
end light;
architecture LogicFunction of light is
begin
f <= (x1 and not x2) or (not x1 and x2);
end LogicFunction;
and save the file again.
Compile with Processing > Start > Start Analysis & Synthesis — or press
Ctrl + K.
The Message window displays the error:
12007 Top-level design entity "alt_ex_1" is undefined
To get rid of the annoying error, delete all the files that were created in
the working directory, and then start all over.
Follow the instructions as above, but this time make sure to replace every
occurrence of alt_ex_1 with light.
In the Message window expect to see something like:
Quartus Analysis & Synthesis was successful. 0 errors, 1 warning
as one of the last lines.
1 Using Altera / Intel Quartus Lite 18.1 on Windows 10, but the
version is likely not important.
References:
- Download Quartus Prime Lite Edition
- Error: top level design entity » » is undefined
- Quartus II Introduction Using VHDL Design
Содержание
- Ошибка Altera Quartus (12007): объект проектирования верхнего уровня «alt_ex_1» не определен.
- Краткий ответ
- Подробный ответ
- Error 12007 top level design entity lab2 is undefined
- Error: top level design entity » » is undefined
- Error 12007 top level design entity lab2 is undefined
- Error: top level design entity » » is undefined
- Error 12007 top level design entity lab2 is undefined
- Error: top level design entity » » is undefined
Ошибка Altera Quartus (12007): объект проектирования верхнего уровня «alt_ex_1» не определен.
Я просмотрел все предыдущие вопросы, и, похоже, ни у кого нет такой простой проблемы, как у меня. Также я искал в Интернете и не нашел решения.
Я новичок в VHDL и пытаюсь скомпилировать простой пример, предоставленный Altera, который выглядит следующим образом:
Я выполнил шаги создания проекта в руководстве по Altera , но когда я пытаюсь скомпилировать проект, я получаю сообщение об ошибке:
В главе Starting a New Project вас попросили назвать ваш проект light . Мне кажется, что вы неправильно выполнили этот шаг и назвали свой проект alt_ex_1 . Вот почему вы получаете ошибку 12007, поскольку компилятор не знает, что является объектом верхнего уровня в вашей разработке.
Чтобы решить эту проблему, вы можете:
- Измените назначение сущности верхнего уровня в Assignments -> Device -> General .
- Установите свой модуль как верхний объект через Project Navigator ( Files -> Set as top-level entity ).
Кстати 1 , 2 , 3 , . — у всех примерно одна и та же проблема.
Моя проблема была связана с компилятором кода Verilog. Но когда я ищу проблему, я всегда видел этот вопрос. Поэтому я решил добавить свое решение, чтобы направлять других. Мне потребовалось много времени, чтобы найти решение. вот что я сделал для решения проблемы. Просто выполните следующие действия (Quartus II 14.0.0); Assignments -> Settings -> Top-Level Entity -> Select your module
Просто наведите указатель мыши на имя файла на панели навигатора проекта и щелкните правой кнопкой, а затем нажмите (установить как объект верхнего уровня). Выполнено.
Краткий ответ
Сообщение об ошибке далеко не тривиально для понимания, но окольным путем оно говорит о том, что не так. Вы (вероятно) используете alt_ex_1.vhd в качестве имени своего файла дизайна.
В Altera Quartus имя файла должно совпадать с именем (верхнего уровня), entity объявленным в коде проекта VHDL.
Что вам нужно сделать, так это изменить имя файла с alt_ex_1.vhd на light.vhd .
Для простоты создайте новый проект с именем light вместо alt_ex_1 .
Подробный ответ
Воспроизвести ошибку просто. Вот что я сделал. 1
После запуска Quartus Prime Lite Edition щелкните File > New Project Wizard. .
Если вы видите Введение , щелкните Next > . Выберите рабочий каталог.
В качестве названия проекта укажите alt_ex_1 . Next > Дважды щелкните, а затем Finish .
Создайте файл дизайна: File > New. .
Под Design Files выберите VHDL File , затем OK .
Далее File > Save As. . Введите или вставьте alt_ex_1.vhd и щелкните Save .
Вставьте код:
и снова сохраните файл.
Компиляция с Processing > Start > Start Analysis & Synthesis — или нажмите Ctrl + K . В окне сообщения отображается ошибка:
Чтобы избавиться от надоедливой ошибки, удалите все файлы, которые были созданы в рабочем каталоге, а затем начните все сначала. Следуйте инструкции, что и выше, но на этот раз необходимо заменить каждое вхождение alt_ex_1 с light .
В окне сообщения ожидайте увидеть что-то вроде:
как одна из последних строк.
1 Использование Altera / Intel Quartus Lite 18.1 в Windows 10, но версия, скорее всего, не важна.
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we have problem in compiling VHDL code in Quartus II software. Every time we compile it shows the Error:top level design entity » file name» is undefined.
We are even taking care of the case sensitivity.
Our file name, new created project name and entity name in the code are all same.
Plz help us regarding this.
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I think this relates to th OPs problem. There seems to be a typo in the supplied file from Altera as part of DE2_tutorialsdesign_files data set has the top level entity/arch named addersubtractor2 in addersubtractor.vhd, it should of course be addersubtractor the file is marked (C) 2005 Altera Corporation.
ENTITY addersubtractor2 IS
GENERIC ( n : INTEGER := 16 ) ;
PORT ( A, B : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;
Clock, Reset, Sel, AddSub : IN STD_LOGIC ;
Z : BUFFER STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;
Overflow: OUT STD_LOGIC ) ;
ARCHITECTURE Behavior OF addersubtractor2 IS.
This section of the file should read (as it did in 8.0sp1 supplied files):
ENTITY addersubtractor IS
GENERIC ( n : INTEGER := 16 ) ;
PORT ( A, B : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;
Clock, Reset, Sel, AddSub : IN STD_LOGIC ;
Z : BUFFER STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;
Overflow: OUT STD_LOGIC ) ;
ARCHITECTURE Behavior OF addersubtractor IS.
This file is marked — (C) 2004 Altera Corporation. All rights reserved.
Looks like a typo possibly, but if you change the top level entity and architecture to match as shown it will compile ok. Not helpful for beginners!
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Hello, guys, thanks for all your efforts,
I encountered the same problem and solved it just now. It was due to the typo of my top level design entity name. A stupid mistake =)
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I strongly suggest to check the spell of the name of your entity.
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I solved this in Quartus II 11.0 by going Assignments > Settings > General and making my Top-level entity the name of my top level Verilog module (not its filename).
e.g. for a file named example.v
module circuit (output f, input x,y,z);
make the Top-level entity «circuit» not «example»
- Mark as New
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save yourself some pain when changing top level entities (for debug) and match your file and module name
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Hello, guys, thanks for all your efforts,
I encountered the same problem and solved it just now. It was due to the typo of my top level design entity name. A stupid mistake =)
your post solved my lot of problems, thank you very much. You made me understand a very important concept.
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Resurrecting an old thread here, but I just had this problem and this thread came up top of a google search. I’ve been using Quartus for 8 months now but have always been copying existing projects, but I recently tried a new project and it was a bit tricky so I have gone through every step and written it up below. Even in this simple led blink program there are 3 places that the project name is mentioned and it must match all these to avoid a «top level design entity» error.
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Error 12007 top level design entity lab2 is undefined
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we have problem in compiling VHDL code in Quartus II software. Every time we compile it shows the Error:top level design entity » file name» is undefined.
We are even taking care of the case sensitivity.
Our file name, new created project name and entity name in the code are all same.
Plz help us regarding this.
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I think this relates to th OPs problem. There seems to be a typo in the supplied file from Altera as part of DE2_tutorialsdesign_files data set has the top level entity/arch named addersubtractor2 in addersubtractor.vhd, it should of course be addersubtractor the file is marked (C) 2005 Altera Corporation.
ENTITY addersubtractor2 IS
GENERIC ( n : INTEGER := 16 ) ;
PORT ( A, B : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;
Clock, Reset, Sel, AddSub : IN STD_LOGIC ;
Z : BUFFER STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;
Overflow: OUT STD_LOGIC ) ;
ARCHITECTURE Behavior OF addersubtractor2 IS.
This section of the file should read (as it did in 8.0sp1 supplied files):
ENTITY addersubtractor IS
GENERIC ( n : INTEGER := 16 ) ;
PORT ( A, B : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;
Clock, Reset, Sel, AddSub : IN STD_LOGIC ;
Z : BUFFER STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;
Overflow: OUT STD_LOGIC ) ;
ARCHITECTURE Behavior OF addersubtractor IS.
This file is marked — (C) 2004 Altera Corporation. All rights reserved.
Looks like a typo possibly, but if you change the top level entity and architecture to match as shown it will compile ok. Not helpful for beginners!
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Hello, guys, thanks for all your efforts,
I encountered the same problem and solved it just now. It was due to the typo of my top level design entity name. A stupid mistake =)
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I strongly suggest to check the spell of the name of your entity.
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I solved this in Quartus II 11.0 by going Assignments > Settings > General and making my Top-level entity the name of my top level Verilog module (not its filename).
e.g. for a file named example.v
module circuit (output f, input x,y,z);
make the Top-level entity «circuit» not «example»
- Mark as New
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save yourself some pain when changing top level entities (for debug) and match your file and module name
- Mark as New
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Hello, guys, thanks for all your efforts,
I encountered the same problem and solved it just now. It was due to the typo of my top level design entity name. A stupid mistake =)
your post solved my lot of problems, thank you very much. You made me understand a very important concept.
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Resurrecting an old thread here, but I just had this problem and this thread came up top of a google search. I’ve been using Quartus for 8 months now but have always been copying existing projects, but I recently tried a new project and it was a bit tricky so I have gone through every step and written it up below. Even in this simple led blink program there are 3 places that the project name is mentioned and it must match all these to avoid a «top level design entity» error.
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Error 12007 top level design entity lab2 is undefined
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we have problem in compiling VHDL code in Quartus II software. Every time we compile it shows the Error:top level design entity » file name» is undefined.
We are even taking care of the case sensitivity.
Our file name, new created project name and entity name in the code are all same.
Plz help us regarding this.
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I think this relates to th OPs problem. There seems to be a typo in the supplied file from Altera as part of DE2_tutorialsdesign_files data set has the top level entity/arch named addersubtractor2 in addersubtractor.vhd, it should of course be addersubtractor the file is marked (C) 2005 Altera Corporation.
ENTITY addersubtractor2 IS
GENERIC ( n : INTEGER := 16 ) ;
PORT ( A, B : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;
Clock, Reset, Sel, AddSub : IN STD_LOGIC ;
Z : BUFFER STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;
Overflow: OUT STD_LOGIC ) ;
ARCHITECTURE Behavior OF addersubtractor2 IS.
This section of the file should read (as it did in 8.0sp1 supplied files):
ENTITY addersubtractor IS
GENERIC ( n : INTEGER := 16 ) ;
PORT ( A, B : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;
Clock, Reset, Sel, AddSub : IN STD_LOGIC ;
Z : BUFFER STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;
Overflow: OUT STD_LOGIC ) ;
ARCHITECTURE Behavior OF addersubtractor IS.
This file is marked — (C) 2004 Altera Corporation. All rights reserved.
Looks like a typo possibly, but if you change the top level entity and architecture to match as shown it will compile ok. Not helpful for beginners!
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Hello, guys, thanks for all your efforts,
I encountered the same problem and solved it just now. It was due to the typo of my top level design entity name. A stupid mistake =)
- Mark as New
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I strongly suggest to check the spell of the name of your entity.
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I solved this in Quartus II 11.0 by going Assignments > Settings > General and making my Top-level entity the name of my top level Verilog module (not its filename).
e.g. for a file named example.v
module circuit (output f, input x,y,z);
make the Top-level entity «circuit» not «example»
- Mark as New
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save yourself some pain when changing top level entities (for debug) and match your file and module name
- Mark as New
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Hello, guys, thanks for all your efforts,
I encountered the same problem and solved it just now. It was due to the typo of my top level design entity name. A stupid mistake =)
your post solved my lot of problems, thank you very much. You made me understand a very important concept.
- Mark as New
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Resurrecting an old thread here, but I just had this problem and this thread came up top of a google search. I’ve been using Quartus for 8 months now but have always been copying existing projects, but I recently tried a new project and it was a bit tricky so I have gone through every step and written it up below. Even in this simple led blink program there are 3 places that the project name is mentioned and it must match all these to avoid a «top level design entity» error.
Источник
Я просмотрел все предыдущие вопросы, и, похоже, ни у кого нет такой простой проблемы, как у меня. Также я искал в Интернете и не нашел решения.
Я новичок в VHDL и пытаюсь скомпилировать простой пример, предоставленный Altera, который выглядит следующим образом:
library ieee;
use ieee.std_logic_1164.all;
entity light is
port(x1, x2: in std_logic;
f: out std_logic);
end light;
architecture LogicFunction of light is
begin
f <= (x1 and not x2) or (not x1 and x2);
end LogicFunction;
Я выполнил шаги создания проекта в руководстве Altera, но когда я пытаюсь скомпилировать проект, я получаю сообщение об ошибке:
Error (12007): Top-level design entity "alt_ex_1" is undefined
4 ответа
Лучший ответ
В главе Starting a New Project вас попросили назвать ваш проект light. Мне кажется, что вы неправильно выполнили этот шаг и назвали свой проект alt_ex_1. Вот почему вы получаете ошибку 12007, поскольку компилятор не знает, что является объектом верхнего уровня в вашей разработке.
Чтобы решить эту проблему, вы можете:
- Измените назначение сущности верхнего уровня в
Assignments -> Device -> General. - Установите свой модуль как верхний объект через
Project Navigator(Files -> Set as top-level entity).
Кстати, 1, 2, 3, … — все об одной и той же проблеме.
13
Qiu
14 Сен 2014 в 20:17
Краткий ответ
Error (12007): Top-level design entity "alt_ex_1" is undefined
Сообщение об ошибке далеко не тривиально для понимания, но в обходной манере так, как он показывает , что не так. Вы (вероятно) используете alt_ex_1.vhd в качестве имени файла дизайна.
В Altera Quartus имя файла должно совпадать с именем (верхний уровень) entity объявлен в коде проектирования VHDL.
Что вам нужно сделать, так это изменить имя файла с alt_ex_1.vhd на light.vhd.
Для простоты создайте новый проект с именем light вместо alt_ex_1.
Подробный ответ
1
После запуска Quartus Prime Lite Edition нажмите File> New Project Wizard....
Если вы видите Введение , нажмите Next >. Выберите рабочий каталог.
В качестве названия проекта введите alt_ex_1. Дважды нажмите Next >, а затем Finish.
Создайте файл дизайна: File> New....
В разделе Design Files выберите VHDL File, затем ОК .
Далее File> Save As.... Введите или вставьте alt_ex_1.vhd и нажмите Save.
Вставьте код:
library ieee;
use ieee.std_logic_1164.all;
entity light is
port(x1, x2: in std_logic;
f: out std_logic);
end light;
architecture LogicFunction of light is
begin
f <= (x1 and not x2) or (not x1 and x2);
end LogicFunction;
И снова сохраните файл.
Скомпилируйте с помощью Processing> Start> Start Analysis & Synthesis — или нажмите Ctrl + K . В окне Сообщение отображается ошибка:
12007 Top-level design entity "alt_ex_1" is undefined
Чтобы избавиться от надоедливой ошибки, удалите все файлы, которые были созданы в рабочий каталог, а затем начать все сначала. Следуйте инструкциям, приведенным выше, но на этот раз не забудьте заменить все появление alt_ex_1 с light.
В окне Сообщение ожидайте увидеть что-то вроде:
Quartus Analysis & Synthesis was successful. 0 errors, 1 warning
Как одна из последних строк.
1
Ссылки:
- Скачать Quartus Prime Lite Edition
- Ошибка: объект проектирования верхнего уровня «» не определен
- Введение в Quartus II с использованием VHDL-дизайна
0
Henke
29 Мар 2021 в 18:37
Просто наведите указатель мыши на имя файла на панели навигатора проекта и щелкните правой кнопкой, а затем нажмите (установить как объект верхнего уровня). Сделанный.
2
Hender
1 Май 2015 в 02:30
Моя проблема была связана с компилятором кода Verilog. Но когда я ищу проблему, я всегда видел этот вопрос. Поэтому я решил добавить свое решение, чтобы направлять других. Мне потребовалось много времени, чтобы найти решение. вот что я сделал для решения проблемы. Просто выполните следующие действия (Quartus II 14.0.0); Assignments -> Settings -> Top-Level Entity -> Select your module
14
Sabri Meviş
20 Ноя 2014 в 14:29
During: Start Compilation, Start Analysis and Elaboration, Start Analysis and Synthesis
I have no Jtag or PCB fixture yet, so I am intending only to Simulate.
=======================================================================
Error (12007): Top-level design entity «TEI0023_adc-adaq4003_20200716» is undefined
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning
Error: Peak virtual memory: 565 megabytes
Error: Processing ended: Sun Sep 12 15:43:30 2021
Error: Elapsed time: 00:00:13
Error: Total CPU time (on all processors): 00:00:33
Error (293001): Quartus Prime Full Compilation was unsuccessful. 3 errors, 1 warning
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Solution 1
In chapter Starting a New Project, you were asked to call your project light. It seems to me that you didn’t follow that step correctly and name your project alt_ex_1. That’s why you’re getting 12007 error, since the compiler has no idea what is the top-level entity in you design.
To solve that problem you can:
- Change the top-level entity assignment in
Assignments -> Device -> General. - Set your module as top-entity via
Project Navigator(Files -> Set as top-level entity).
Btw 1, 2, 3, … — all about the same problem.
Solution 2
My problem was about verilog code compiler. But when I search for problem, I always saw this question. So I decided to add my solution too to guide others. It took me much time to find solution. here is what I had done to solve the problem.Just follow these steps (Quartus II 14.0.0) ; Assignments -> Settings -> Top-Level Entity ->Select your module
Solution 3
Just put the pointer over the file name in the project navigator panel and click with right button and then push on (set as top-level entity).
Done.
Comments
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I’ve looked at all the previous questions and no one seems to have a problem
as simple as mine. Also I’ve searched the web and can’t find a solution.I’m new to VHDL and am trying to compile the simple example provided
by Altera, which is as follows:library ieee; use ieee.std_logic_1164.all; entity light is port(x1, x2: in std_logic; f: out std_logic); end light; architecture LogicFunction of light is begin f <= (x1 and not x2) or (not x1 and x2); end LogicFunction;I followed the project creation steps in the Altera tutorial,
but when I try to compile the project I get the error:Error (12007): Top-level design entity "alt_ex_1" is undefined