Working with 2014 version of Quartus II software (web edition), I receive the error 10170 when compiling the following code:
module shifter16 (A, H_sel, H)
input [15:0]A;
input H_sel;
output [15:0]H;
reg [15:0] H;
always @ (A or H_sel)
begin
if (H_sel)
H={A[14:0],1'b0};
else
H={A[15],A[15:1]};
end
endmodule
Error received:
Error (10170): Verilog HDL syntax error at shifter16.v(2) near text «input»; expecting «;»
Qiu
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asked Apr 22, 2014 at 17:26
You need a semicolon at the end of the first line:
module shifter16 (A, H_sel, H);
answered Apr 22, 2014 at 17:39
AriAri
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0
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Article ID: 000075173
Content Type: Error Messages
Last Reviewed: 11/24/2014
Error (10170): Verilog HDL syntax error at <Verilog_file>.v(line_number) near text «,»; expecting an operand
Environment
Version Found: 13.1
Due to a problem in the Quartus® II software version 13.1 and later, you may get the following error when compiling a Verilog HDL file that has converted from a Block Design File (.bdf).
The cause of the error is due to the generated Verilog HDL file has a extra comma in the port connections.
To workaround the error, manually delete the extra comma in the <Verilog_file>.v(line_number).
This problem is schedule to be fixed in future release of the Quartus II software.
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Hi, i got some trouble for the code i developed:
when i execute this code:
if(rst==1’b1)
begin
38. cs [0] = 4’b0;
39. cs [1] = 4’b0;
40. cs [2] = 4’b0;
41. cs [3] = 4’b0;
42. cs [4] = 4’b0;
43. s [5] = 4’b0;
end
then compile and i got that syntax:
Error (10170): Verilog HDL syntax error at digitalclock.v(39) near text «=»; expecting «.», or an identifier
Error (10170): Verilog HDL syntax error at digitalclock.v(40) near text «=»; expecting «.», or an identifier
Error (10170): Verilog HDL syntax error at digitalclock.v(41) near text «=»; expecting «.», or an identifier
Error (10170): Verilog HDL syntax error at digitalclock.v(42) near text «=»; expecting «.», or an identifier
Error (10170): Verilog HDL syntax error at digitalclock.v(43) near text «=»; expecting «.», or an identifier
please note line 38!
please help me solved this error, thank you! 
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Article ID: 000074032
Content Type: Error Messages
Last Reviewed: 12/13/2019
Error (10170): Verilog HDL syntax error at source.sv(7) near text: «XXX»; expecting «)
Environment
Bug ID: 14010471351
Version Found: 19.1
Due to a problem in the Intel® Quartus® Prime Standard edition software version 19.1 you will observe this error when you use instantiated typedef enum in a module with an explicit nettype.
To work around this problem, remove the explicit nettype from the module definition. If the Verilog source is part of a library and cannot change, use VERILOG_MACRO with ifdef statement to contain the Verilog code that is handled by the Intel® Quartus® Prime Standard edition software. The name of the VERILOG_MACRO can be defined in the Intel Quartus Setting File (.qsf) with the following assignment:
set_global_assignment -name VERILOG_MACRO «<USER_DEFINED>=1»
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The reason for your syntax error is that you cannot just write:
product [7:4] = 4'b0000;
you must write
assign product [7:4] = 4'b0000;
But, unless you are using System-Verilog (and your old-fashioned style of coding suggests you are not), you will find that
assign product [7:4] = 4'b0000;
will not compile either, because the target of an assign statement must be a wire, not a reg. And if you change product to a wire, you will then find these statements give you and error:
product = product >> 1; // shift right, and assign the most significant bit to 0
product[7:3] = product[7:3] + multiplicand[4:0]; // add 5-bits so we can handle the carry-out
and
product = product >> 1; // shift to the right
because you cannot assign to a wire in an always (or initial) block.
You seem to be designing some kind of shift-and-add multiplier and presumably want to initialise product at the beginning of the calculation. (Assuming you sort the syntax) the lines
(assign) product [7:4] = 4'b0000;
(assign) product [3:0] = multiplier [3:0];
drive product continuously, for all time; they do not initialise product. You are designing hardware here, not writing software.